UART学习笔记

串口(UART)

DIV_VAL=(PCLK/(bpsx16))−1

35=115200/66.5/16-1

 

 

查看芯片手册：

GPACON0x7F008000R/WPortAConfigurationRegister0x0000

 

 

GPA0[3:0]0000=Input0001=Output

0010=UARTRXD[0]0011=Reserved

0100=Reserved0101=Reserved

0110=Reserved0111=ExternalInterruptGroup1[0]

0000

GPA1[7:4]0000=Input0001=Output

0010=UARTTXD[0]0011=Reserved

0100=Reserved0101=Reserved

0110=Reserved0111=ExternalInterruptGroup1[1]

0000

 

 

ULCON00x7F005000R/WUARTchannel0linecontrolregister0x00

 

 

Reserved[7]0

Infra-RedMode[6]DeterminewhetherornottousetheInfra-Redmode.

0=Normalmodeoperation

1=Infra-RedTx/Rxmode

0

ParityMode[5:3]Specifythetypeofparitygenerationandcheckingduring

UARTtransmitandreceiveoperation.

0xx=Noparity

100=Oddparity

101=Evenparity

110=Parityforced/checkedas1

111=Parityforced/checkedas0

000

NumberofStopBit[2]Specifyhowmanystopbitsaretobeusedforend-of-frame

signal.

0=Onestopbitperframe

1=Twostopbitperframe

0

WordLength[1:0]Indicatethenumberofdatabitstobetransmittedorreceived

perframe.

00=5-bit01=6-bit

10=7-bit11=8-bit

UCON00x7F005004R/WUARTchannel0controlregister0x00

TransmitMode[3:2]DeterminewhichfunctioniscurrentlyabletowriteTxdatatothe

UARTtransmitbufferregister.

00=Disable

01=Interruptrequestorpollingmode

10=DMArequest(DMA_UART0)

11=DMArequest(DMA_UART1)

00

ReceiveMode[1:0]DeterminewhichfunctioniscurrentlyabletoreaddatafromUART

receivebufferregister.

00=Disable

01=Interruptrequestorpollingmode

10=DMArequest(DMA_UART0)

11=DMArequest(DMA_UART1)

 

 

UFCON00x7F005008R/WUARTchannel0FIFOcontrolregister0x0

FIFOEnable[0]0=Disable1=Enable0

 

UMCON00x7F00500CR/WUARTchannel0Modemcontrolregister0x0

 

DIV_VAL=UBRDIVn+(numof1’sinUDIVSLOTn)/16

DIV_VAL=(PCLK/(bpsx16))−1

Forexample,ifthebaud-rateis115200bpsandEXT_UCLK0isUARTbaud-rateclockand40MHz,UBRDIVn

andUDIVSLOTnare:

 

DIV_VAL=(40000000/(115200x16))-1=21.7-1

=20.7

UBRDIVn=20(integerpartofDIV_VAL)

(numof1’sinUDIVSLOTn)/16=0.7

then,(numof1’sinUDIVSLOTn)=11

 

66.5mhz*10(6)=66500000

 

UBRDIV00x7F005028R/WBaudratedivisiorregister00x0000

UDIVSLOT00x7F00502CR/WBaudratedivisiorregister00x0000

 

UFSTAT00x7F005018RUARTchannel0FIFOstatusregister0x00

 

TxFIFOFull[14]Setto1automaticallywhenevertransmitFIFOisfull

duringtransmitoperation

0=0-byte≤TxFIFOdata≤63-byte

1=Full

0

TxFIFOCount[13:8]NumberofdatainTxFIFO0

Reserved[7]0

RxFIFOFull[6]Setto1automaticallywheneverreceiveFIFOisfullduring

receiveoperation

0=0-byte≤RxFIFOdata≤63-byte

1=Full

0

RxFIFOCount[5:0]NumberofdatainRxFIFO0

URXH00x7F005024RUARTchannel0receivebufferregister0x00

UTXH00x7F005020WUARTchannel0transmitbufferregister-

 

TxFIFOFull[14]Setto1automaticallywhenevertransmitFIFOisfull

duringtransmitoperation

0=0-byte≤TxFIFOdata≤63-byte

1=Full

示例代码如下：

 

#defineULCON0(*((volatileunsignedlong*)0x7F005000))

#defineUCON0(*((volatileunsignedlong*)0x7F005004))

#defineUFCON0(*((volatileunsignedlong*)0x7F005008))

#defineUMCON0(*((volatileunsignedlong*)0x7F00500C))

#defineUTRSTAT0(*((volatileunsignedlong*)0x7F005010))

#defineUFSTAT0(*((volatileunsignedlong*)0x7F005018))

#defineUTXH0(*((volatileunsignedchar*)0x7F005020))

#defineURXH0(*((volatileunsignedchar*)0x7F005024))

#defineUBRDIV0(*((volatileunsignedshort*)0x7F005028))

#defineUDIVSLOT0(*((volatileunsignedshort*)0x7F00502C))

 

#defineGPACON(*((volatileunsignedlong*)0x7F008000))

 

 

voidinit_uart(void)

{

/*将GPACON的前八位清零*/

/*10101010*/

/*00000000（~0xff）*/

/*--------------*/

/*00000000*/

 

GPACON&=~0xff;

/*设GPACON初值*/

GPACON|=0x22;

 

/*ULCON0*/

ULCON0=0x3;/*数据位:8,无较验,停止位:1,8n1*/

UCON0=0x5;/*使能UART发送、接收*/

UFCON0=0x01;/*FIFOENABLE*/

 

UMCON0=0;

 

/*波特率*/

/*DIV_VAL=(PCLK/(bpsx16))-1

*bps=57600

*DIV_VAL=(66500000/(115200x16))-1

*=35.08

*/

UBRDIV0=35;

 

/*x/16=0.08

*x=1

*/

UDIVSLOT0=0x1;

 

}

 

chargetchar(void)

{

while((UFSTAT0&(1<<6))==0&&(UFSTAT0&0x3f)==0);

returnURXH0;

}

 

voidputchar(charc)

{

while((UFSTAT0&(1<<14));

UTXH0=c;

}