386：第2篇

 

从80386开始，包括更高的x86寄存器，还包括一些非正式寄存器，也称为Undocumented registers。

 

非正式寄存器

非正式寄存器分为控制寄存器（control registers）, 调试寄存器（debug registers）, 测试寄存器（test registers）以及保护模式分段寄存器（protected mode segmentation registers）

 

控制寄存器

CR0

Bit(s)     Label    Description

0           PE       Protected Mode Enable

1           MP      Monitor Co-Processor

2           EM      Emulation

3           TS       Task Switched

4           ET       Extension Type

5           NE       Numeric Error

6-15       0         Reserved

16          WP     Write Protect

17          0         Reserved

18         AM       Alignment Mask

19-28     0          Reserved

29         NW       Not-Write Through

30         CD        Cache Disable

31         PG        Paging

 

CR2

CR3

CR4

CR8

 

 

 

CR1

CR5-7

CR9-15

 

调试寄存器

DR0 - DR3

DR6

 

DR7

 

测试寄存器

TR3 - TR5

TR6

 

TR7

 

保护模式分段寄存器

保护模式分段寄存器在文档手册中称为内存管理寄存器（Memory-Management Register）

 

 

 

GDTR

GDTR（Global Descriptor Table Register，全局描述符表寄存器）

GDTR寄存器在32位模式下，即保护模式下是个48位的寄存器，低16位表示GDT的大小，字节数，高32位表示GDT的基地址。

在64位模式下，GDTR寄存器是个80位的寄存器，低16位表示GDT的大小，字节数，高64位表示DT的基地址。

 

 

写道

 

4 4 3 3 3 2 2 1 1 
7 0 9 2 1 4 3 6 5 8 7 0 
+--------+--------+--------+--------+--------+--------+
| base address | limit |
+--------+--------+--------+--------+--------+--------+
|<---------high 4 bytes------------>|<--low 2 bytes-->|

 

 

写道

 

4 4 3 3 3 2 2 1 1 
7 0 9 2 1 4 3 6 5 8 7 0 
+--------+--------+--------+--------+--------+--------+
|00000000 base address | limit |
+--------+--------+--------+--------+--------+--------+
|<---------high 4 bytes------------>|<--low 2 bytes-->|

 

 

写道

 

7 7 6 5 4 4 4 3 3 3 2 2 1 1 
9 2 4 6 8 7 0 9 2 1 4 3 6 5 8 7 0 
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+
| base address | limit |
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+
|<---------------------------high 8 bytes------------------------------>|<--low 2 bytes-->|

 

 

 

LDTR

LDTR（Local Descriptor Table Register，局部描述符表寄存器）

 

TR

TR(Task Register, 任务寄存器)

写道

The task register holds the 16-bit segment selector, base address (32 bits in protected mode; 64 bits in IA-32e mode), segment limit, and descriptor attributes for the TSS of the current task. The selector references the TSS descriptor in the GDT. The base address specifies the linear address of byte 0 of the TSS; the segment limit specifies the number of bytes in the TSS. See also: Section 7.2.4, “Task Register.”

 

 

写道

The task register holds the 16-bit segment selector and the entire segment descriptor (32-bit base address (64 bits in IA-32e mode), 16-bit segment limit, and descriptor attributes) for the TSS of the current task (see Figure 2-6).

任务寄存器（TR，Task Register）保存16位段选择子和整个段描述符（32位基地址，在IA-32e模式下是64位基地址，16位segment limit以及描述符属性）

 

任务寄存器由可见部分（visible part）和不可见部分（invisible part），可见部分可以被软件读取和修改，不可见部分由处理器维护，不可被软件访问。

 

可见部分：16位段选择子

 

处理器使用不可见部分缓存段描述符，在任务寄存器中缓存这个使得任务执行更高效。

 

写道

The LTR (load task register) and STR (store task register) instructions load and read the visible portion of the task register:
The LTR instruction loads a segment selector (source operand) into the task register that points to a TSS descriptor in the GDT. It then loads the invisible portion of the task register with information from the TSS descriptor. LTR is a privileged instruction that may be executed only when the CPL is 0. It’s used during system initialization to put an initial value in the task register. Afterwards, the contents of the task register are changed implicitly when a task switch occurs.
The STR (store task register) instruction stores the visible portion of the task register in a general-purpose register or memory. This instruction can be executed by code running at any privilege level in order to identify the currently running task. However, it is normally used only by operating system software. (If CR4.UMIP = 1, STR can be executed only when CPL = 0.)

 

 

IDTR

IDTR（Interrupt Descriptor Table Register，中断描述符表寄存器）

写道

4 4 3 3 3 2 2 1 1 
7 0 9 2 1 4 3 6 5 8 7 0 
+--------+--------+--------+--------+--------+--------+
| base address | limit |
+--------+--------+--------+--------+--------+--------+
|<---------high 4 bytes------------>|<--low 2 bytes-->|

 

写道

4 4 3 3 3 2 2 1 1 
7 0 9 2 1 4 3 6 5 8 7 0 
+--------+--------+--------+--------+--------+--------+
|00000000 base address | limit |
+--------+--------+--------+--------+--------+--------+
|<---------high 4 bytes------------>|<--low 2 bytes-->|

 

写道

7 7 6 5 4 4 4 3 3 3 2 2 1 1 
9 2 4 6 8 7 0 9 2 1 4 3 6 5 8 7 0 
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+
| base address | limit |
+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+
|<---------------------------high 8 bytes------------------------------>|<--low 2 bytes-->|

 
 

除了CPU有寄存器，很多外设，比如显卡，网卡等内部都有自己的寄存器。只是这些寄存器都不能直接访问。

 

POPF/POPFD/POPFQ — Pop Stack into EFLAGS Register也会影响CF标志。这在文档手册没有没有反应。