CPU C-states

 

1:ACPI

http://en.wikipedia.org/wiki/Advanced_Configuration_and_Power_Interface

 

 

2：What is difference between deep and deeper sleep states?

http://www.intel.com/support/processors/sb/CS-028739.htm

 

 

3：Everything You Need to Know About the CPU C-States Power Saving Modes

http://www.hardwaresecrets.com/article/Everything-You-Need-to-Know-About-the-CPU-C-States-Power-Saving-Modes/611

 

 

4：CPU Power States (C-States)

http://www.techarp.com/showarticle.aspx?artno=420&pgno=5

 

 

 

CPU C-states occur in the global system G0 state. Users may not notice it when they are using the computer, unless monitoring tools like CPU-Z is used to inspect the clock speed and voltage. C-state implementations are processor-specific. Mobile processors usually have more C-states than desktop processors. For example, the mobile Core 2 Duo processor (Merom) supports C0 to C4 states, whereas the desktop Core 2 Duo processor (Conroe) only supports C0 and C1 states.

 

 

C0 State (Active)

• This is the CPU's maximum working state, where it is actively accepting instructions and processing data.
• Power saving is virtually zero, unless the CPU has P-state power management enabled.

C1 State (Halt)

• It is simply done by executing the assembly instruction “HLT” (Halt).
• This will stop the instruction pipeline within the CPU from executing any instructions.
• Wake-up time is ultra fast (only about 10 nano seconds).
• The CPU is able to save up to 70% of its maximum power consumption.
• All modern processors must support this power state.

C2 State (Stop Grant)

• The processor core clock and platform I/O buffers are gated.
• In other words, the clock does not exist in the processor execution engines and I/O buffers.
• The benefit over C1 is that the C2 state is able to save 70% of the CPU's maximum power plus some platform power.
• However, the transition time from C2 to C0 is 10 times more (~100 nano seconds).

C3 State (Deep Sleep)

• The bus clock and PLLs are gated.
• In a multi-processor system, the processors no longer handle FSB snoops to maintain cache coherency. Cache contents are invalidated.
• In a single-processor system, memory transactions are prohibited but cache contents are not invalidated.
• CPU still saves around 70% power, but the platform power will be reduced even more than C2.
• Wake up time is 500 times longer than C2 (about 50 micro seconds).

C4 State (Deeper Sleep)

• It is similar to the C3 state, but with two main differences.
• First, the core voltage is reduced to a very low level (less than 1.0V) to decrease current leakage.
• Second, data stored in the L2 cache will be reduced bit by bit over time.
• The CPU can save around 98% of its maximum power.
• Wake-up time is slower, but still much lower than 1 second (~160 micro seconds).

C5 State

• When the data in the L2 cache is reduced to zero.
• Wake-up time is more than 200 micro seconds.

C6 State

• New power management feature in Penryn.
• When the L2 cache contents are shrunk to zero, the CPU will go into an even lower core voltage.
• CPU context is no longer preserved.
• Power consumption is currently unknown. Should be near zero.
• Wake-up time is currently unknown.

 

5：C-States In Multi-Core Processors

http://www.techarp.com/showarticle.aspx?artno=420&pgno=6

 

 

In a multi-core processor, there can be multiple C-states in each core, but only one processor C-state is enabled at one time. The processor C-state is equal to the highest C-state of any processing core. Let's say the processor C-state is Cx, and core C-state is CCx, the formula for determining the processor C-state would be :

Cx = max (CCx1, CCx2, CCx3……, CCxn)

Here are some examples :

CPU In C0 State	CPU In C1 State	CPU In C2 State
max (CC0, CC3) = CC0	max (CC1, CC3) = CC1	max (CC2, CC3) = CC02
CPU In C3 State	CPU In C3 State	CPU In C4 State
max (CC3, CC3) = CC3	max (CC4, CC3) = CC3	max (CC4, CC4) = CC4

CPU Power States Summary

Power State	Execution	Wake-Up Time	CPU Power	Platform	Core Voltage	Cache Shrink	Loss Of Context
C0	Yes	0ns	large	normal	normal	no	no
C1	No	10ns	30%	normal	normal	no	no
C2	No	100ns	30%	no I/O buffer	normal	no	no
C3	No	50,000ns	30%	I/O + no snoop	normal	no	no
C4	No	160,000ns	2%	I/O + no snoop	C4_VID	yes	no
C5	No	200,000ns	N/A	N/A	C4_VID	L2 = 0KB	no
C6	No	N/A	N/A	N/A	C6_VID	L2 = 0KB	yes